The use of advanced semiconductor lithography and etching processes has enabled reduction in the dimensions of semiconductor devices and a concomitant increase in device operating speed. However, this reduction in dimensions causes a corresponding decrease in the cross-sectional area of interconnect regions, thus leading to an increase in interconnection time delay resulting from both material and circuit parameters. A solution to the increase in interconnection time delay is to place a metal silicide layer on top of a doped polycrystalline silicon in order to lower the sheet resistance of the polycrystalline silicon interconnections and gain increased circuit speed. See, for example, U.S. Pat. No. 4,180,596, issued Dec. 25, 1979 to Crowder et al.
In a salicide (self-aligned silicide) process, polysilicon is deposited on a wafer and patterned to form a gate electrode structure, and insulating sidewall spacers are then formed so as to passivate the sidewalls of the gate electrode structure. Dopants are then implanted to form source and drain regions in the wafer, and the dopants are electrically activated by a high temperature anneal. Next, a thin metal film is deposited over the entire wafer, and the wafer is heated, such as in a nitrogen ambient, so as to selectively react the metal with exposed silicon to form silicide contacts over the source, gate and drain silicon. During such heating, the metal over the insulating sidewall spacers is converted to metal nitride, and the metal nitride is selectively etched and removed. A high temperature anneal is then used to reduce the resistivity of the silicide.
Addition of the metal silicide layer lowers the sheet resistance and thereby increases the circuit speed. However, for the reasons outlined hereinbelow, it is necessary for the metal silicide to demonstrate thermal stability during subsequent annealing.
A key technological problem is the agglomeration of metal silicide upon high temperature annealing, i.e., annealing at temperatures greater than approximately 800 degrees C. Agglomeration is a condition in which the metal silicide film has discontinuities caused by silicon diffusion and grain growth. At elevated temperatures, silicon within and under the metal silicide diffuse and eventually coalesce to form large silicon grains which break the continuity of the original metal silicide film. Accordingly, a narrow conductor constructed with an agglomerated silicide tends to show a significant increase in average sheet resistance. In this regard, localized breaks in the film can have very high resistance if the silicide is completely severed across the width of the line. As such, in high speed circuit applications requiring low resistance silicide conductors, agglomeration can result in performance degradation or total functional failure.
An objective in device manufacturing processing is therefore to identify a thermal process window in which the low resistance silicide will form and not agglomerate. This process window must be large enough to accommodate temperature and time variations without resulting in incomplete silicide conversion or agglomeration. The problem is highlighted, for example, when forming titanium silicide (TiSi.sub.2) on P+ doped polysilicon. The activation energy for forming low resistivity C54 TiSi.sub.2 on P+ doped polysilicon is higher than for forming low resistivity C54 TiSi.sub.2 on undoped polysilicon, and this increased activation energy causes the manufacturing process window to shrink even further.
A related thermal stability problem of silicide conductors occurs specifically on poly/silicide conductors which are used for gates on N-type or P-type MOS transistors. Upon high temperature anneals, the condition of agglomeration can extend to a condition referred to as "inversion", in which the silicide and underlying polysilicon exchange position. At high temperatures, silicon and silicide diffuse in opposite directions which eventually results in the silicide coming into contact with the thin gate silicon oxide of the MOS device. The metals in the silicide tend to poison, i.e., cause deterioration of, the gate oxide which results in a lowering of the dielectric breakdown and eventual current leakage upon applied voltage. This quickly leads to device and circuit failure at high speed or DC applications. In this regard, physical analysis of TiSi.sub.2 salicide conductors revealed the presence of the C49 TiSi.sub.2 phase at the failing sites. This suggests that incomplete conversion to the low resistance C54 phase can aid the inversion process at high temperature. Agglomeration and inversion are conditions which usually occur together, with the latter requiring higher and/or longer anneal temperatures.
Current ULSI manufacturing processes utilize Rapid Thermal Annealing (RTA) to widen the process window for low resistivity silicide films by allowing the use of high temperature and shorter annealing times. The higher annealing temperatures attainable with RTA change the rate of transformation and improve the formation of low resistance silicide. Shorter annealing times decrease the tendencies for agglomeration. A limitation to RTA, however, is that as linewidths and diffusions are decreased below 0.5 um, the process window for low resistivity silicide formation without agglomeration disappears.
Other manufacturing processes have increased the thickness of silicide film to suppress the tendency of the film to agglomerate. However, for geometries below 0.5 um, a greater thickness of silicide film presents an aggressive aspect ratio that challenges the abilities of the subsequent insulator fill deposition.
Still other manufacturing processes rely on limiting the annealing temperature to below 850 degrees C. and limiting the overall thermal budget.
Accordingly, it is desirable to promote the formation of low resistance silicides and prevent agglomeration of the film during high temperature annealing. Furthermore, a method of manufacturing a silicide structure is necessary such that the metal atoms of a refractory metal or metal silicide are prevented from diffusing through the polysilicon and into the gate oxide during subsequent heat treatments.